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CY7B995
2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer
Features
* 2.5V or 3.3V operation * Split output bank power supplies * Output frequency range: 6 MHz to 200 MHz * Output-output skew < 100 ps * Cycle-cycle jitter <100 ps * 2% max output duty cycle * Selectable output drive strength * Selectable positive or negative edge synchronization * Eight LVTTL outputs driving 50 terminated lines * LVCMOS/LVTTL over-voltage tolerant reference input * Selectable phase-locked loop (PLL) frequency range and lock indicator * Phase adjustments in 625/1250 ps steps up to 7.5 ns * (1-6,8,10,12) x multiply and (1/2,1/4)x divide ratios * Spread-Spectrum-compatible * Power-down mode * Selectable reference divider * Industrial temperature range: -40C to +85C * 44-pin TQFP package
Description
The CY7B995 RoboClock is a low-voltage, low-power, eight-output, 200-MHz clock driver. It features output phase programmability which is necessary to optimize the timing of high-performance computer and communication systems. The user can program both the frequency and the phase of the output banks through nF[0:1] and DS[0:1] pins. The adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock. Any one of the outputs can be connected to feedback input to achieve different reference frequency multiplication and divide ratios and zero input-output delay. The device also features split output bank power supplies which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the three-level PE/HD pin controls the synchronization of the output signals to either the rising or the falling edge of the reference clock and selects the drive strength of the output buffers. The high drive option (PE/HD = MID) increases the output current from 12 mA to 24 mA (3.3V).
Block Diagram
TEST PE/HD PD#/DIV REF
3
Pin Configuration
FS VDDQ1
FS VDD REF
VSS TES T 2F1 2F0 VDD VDDQ1
4F0
3F1 3F0
/R /N
3 3
3
3
3
PLL
FB DS1:0 1F1:0
3 3 Phase Select
LOCK
1Q0 1Q1
3
2Q0
Phase Select
2F1:0
3
2Q1
3F1:0
3 3
Phase Select and /K
3Q0 3Q1 VDDQ3
4F1 1 sOE# 2 PD#/DIV 3 PE/HD 4 VDDQ4 5 VDDQ4 6 4Q1 7 4Q0 8 VSS 9 VSS 10 VSS 11
44 43 42 41 40 39 38 37 36 35 34
CY7B995
12 13 14 15 16 17 18 19 20 21 22 3Q1 3Q0 VDDQ3 VDDQ3 FB 2Q1 2Q0 VSS VSS
4F1:0
3 3
Phase Select and /M
4Q0 4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation Document #: 38-07337 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised February 24, 2004
1F1 33 1F0 32 DS1 31 DS0 30 LOCK 29 VDDQ1 28 VDDQ1 27 1Q0 26 1Q1 25 VSS 24 VSS 23 VSS
CY7B995
Pin Description
Pin 39 17 37 Name REF FB TEST I/O[1] I I I Type LVTTL/LVCMOS LVTTL 3-Level Reference Clock Input. Feedback Input. When MID or HIGH, disables PLL (except for conditions of note 3). REF goes to all outputs. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE/HD = H or M) - 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE# is high, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation. Selects Positive or Negative Edge Control and High or Low output drive strength. When LOW / HIGH the outputs are synchronized with the negative / positive edge of the reference clock, respectively. When at MID level, the output drive strength is increased and the outputs synchronize with the positive edge of the reference clock. Please see Table 9. Select frequency and phase of the outputs. Please see Tables 3, 4, 5, 7, and 8. Selects VCO operating frequency range. Please see Table 6. Four banks of two outputs. Please see Table 5 for frequency settings. Select feedback divider. Please see Table 2. Power down and reference divider control. When LOW, shuts off entire chip. When at MID level, enables the reference divider. Please see Table 1 for settings. PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the input. Power supply for Bank 4 output buffers. Please see Table 10 for supply level constraints Power supply for Bank 3 output buffers. Please see Table 10 for supply level constraints Power supply for Bank 1 and Bank 2 output buffers. Please see Table 10 for supply level constraints Power supply for the internal circuitry. Please see Table 10 for supply level constraints Ground. Table 1. Reference Divider Settings PD#/DIV H M L[4] R-Reference Divider 1 2 N/A Description
2
sOE#
I, PD LVTTL
4
PE/HD
I, PU 3-Level
34, 33, 36, 35, nF[1:0] 43, 42, 1, 44 41 26,27,20,21, 13,14,7,8 32, 31 3 30 5,6 15,16 19,28,29 18,40 FS nQ[1:0] DS[1:0] PD#/DIV LOCK
I I O I
3-Level 3-Level LVTTL 3-Level
I, PU 3-Level O LVTTL
VDDQ4[2] PWR Power VDDQ3 [2] PWR Power VDDQ1[2] VDD[2] PWR Power PWR Power PWR Power
9-12, 22-25, 38 VSS
Device Configuration
The outputs of the CY7B995 can be configured to run at frequencies ranging from 6 MHz to 200 MHz. The feedback input divider is controlled by the 3-level DS[0:1] pins as indicated in Table 2 and the reference input divider is controlled by the 3-level PD#/DIV pin as indicated in Table 1.
Notes: 1. `PD' indicates an internal pull-down and `PU' indicates an internal pull-up. 2. A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin (< 0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. 3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL.
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CY7B995
Table 2. Feedback Divider Settings DS[1:0] LL LM LH ML MM MH HL HM HH N-Feedback Input Divider 2 3 4 5 1 6 8 10 12 Permitted Output Divider Connected to FB 1 or 2 1 1,2 or 4 1 or 2 1,2 or 4 1 or 2 1 or 2 1 1 The divider settings and the FB input to ANY output connection needed to produce various output frequencies are summarized in Table 5. Table 5. Output Frequency Settings Configuration
FB Input Connected to
Output Frequency
1Q[0:1] and 2Q[0:1][6] 3Q[0:1] 4Q[0:1]
1Qn or 2Qn 3Qn 4Qn
(N / R) x (1 / (N / R) x (1 / K) x FREF M) x FREF (N / R) x (K / (N / R) x K x (N / R) x FREF M) x FREF FREF (N / R) x FREF (N / R) x M x (N / R) x (M / (N / R) x FREF K) x FREF FREF
In addition to the reference and feedback dividers, the CY7B995 includes output dividers on Bank3 and Bank4, which are controlled by 3F[1:0] and 4F[1:0] as indicated in Table 3 and 4, respectively. Table 3. Output Divider Settings - Bank 3 3F[1:0] LL HH Other[5] K - Bank3 Output Divider 2 4 1
The 3-level FS control pin setting determines the nominal operating frequency range of the divide-by-one outputs of the device. The CY7B995 PLL operating frequency range that corresponds to each FS level is given in Table 6. Table 6. Frequency Range Select FS L M H PLL Frequency Range 24 to 50MHz 48 to 100MHz 96 to 200MHz
Table 4. Output Divider Settings - Bank 4 4F[1:0] LL Other[5] M- Bank4 Output Divider 2 1
Selectable output skew is in discrete increments of time unit (tU).The value of tU is determined by the FS setting and the maximum nominal frequency. The equation to be used to determine the tU value is as follows: tU = 1 / (fNOM x MF) where MF is a multiplication factor, which is determined by the FS setting as indicated in Table 7.I Table 7. MF Calculation FS L M H MF 32 16 8 fNOM at which tU is 1.0ns(MHz) 31.25 62.5 125
Notes: 4. When PD#/DIV = LOW, the device enters power-down mode 5. These states are used to program the phase of the respective banks. Please see Table 7 and Table 8. 6. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency (FNOM) at a given reference frequency (FREF) and divider and feedback configuration. The user must select a configuration and a reference frequency that will generate a VCO frequency that is within the range specified by FS pin. Please see Table 6.
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CY7B995
Table 8. Output Skew Settings nF[1:0] LL[7] LM LH ML MM MH HL HM HH Skew (1Q[0:1],2Q[0:1]) -4tU -3tU -2tU -1tU Zero Skew +1tU +2tU +3tU +4tU Skew (3Q[0:1]) Divide By 2 -6tU -4tU -2tU Zero Skew +2tU +4tU +6tU Divide By 4 Skew (4Q[0:1]) Divide By 2 -6tU -4tU -2tU Zero Skew +2tU +4tU +6tU Inverted[8] The CY7B995 features split power supply buses for Banks 1 and 2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V and 2.5V output signals from one device. The core power supply (VDD) must be set a level which is equal or higher than that on any one of the output power supplies. Table 10.Power Supply Constraints VDD 3.3V 2.5V VDDQ1[10] 3.3V or 2.5V 2.5V VDDQ3[10] 3.3V or 2.5V 2.5V VDDQ4[10] 3.3V or 2.5V 2.5V
Governing Agencies
The following agencies provide specifications that apply to the CY7B995. The agency name and relevant specification is listed below. Table 11. Agency Name JEDEC IEEE UL-194_V0 MIL Specification JESD 51 (Theta JA) JESD 65 (Skew, Jitter) 1596.3 (Jiter Specs) 94 (Moisture Grading) 883E Method 1012.1 (Therma Theta JC)
In addition to determining whether the outputs synchronize to the rising or the falling edge of the reference signal, the 3-level PE/HD pin controls the output buffer drive strength as indicated in Table 9. Table 9. PE/HD Settings PE/HD L M H Synchronization Negative Positive Positive Output Drive Strength[9] Low Drive High Drive Low Drive
Absolute Maximum Conditions
Parameter VDD VDD VIN(MIN) VIN(MAX) VREF(MAX) VREF(MAX) TS TA TJ OJC OJA ESDHBM UL-94 MSL FIT Description Operating Voltage Operating Voltage Input Voltage Input Voltage Reference Input Voltage Reference Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Failure in Time Manufacturing Testing Condition Functional @ 2.5V 5% Functional @ 3.3V 10% Relative to VSS Relative to VDD VDD = 3.3V VDD = 2.5V Non Functional Functional Functional Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 @1/8 in. -65 -40 - - - 2000 V-0 1 10 ppm Min. 2.25 2.97 VSS-0.3 - Max. 2.75 3.63 - VDD+0.3 5.5 4.6 +150 +85 155 42 74 - Unit V V V V V V C C C C/W C/W V
Notes: 7. LL disables outputs if TEST = MID and sOE# = HIGH. 8. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID, sOE# disables them LOW when PE/HD = LOW. 9. Please refer to "DC Parameters" section for IOH/IOL specifications. 10. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V and VDDQ4 = 2.5V.
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CY7B995
DC Specifications @ 2.5V
.
Parameter VDD VIL VIH VIHH[11] VIMM[11] VILL[11] IIL I3 IPU IPD VOL
Description 2.5 Operating Voltage Input LOW Voltage Input HIGH Voltage Input HIGH Voltage Input MID Voltage Input LOW Voltage Input Leakage Current 2.5V 5%
Conditions
Min. 2.375 - 1.7 VDD - -0.4 VDD/2 - 0.2 - -5 - -50 -200 -25 - - - 2.0 2.0 2.0 - 10(typ.) 150 4
Max. 2.625 0.7 - - VDD/2 + 0.2 0.4 5 200 50 - - 100 0.4 0.4 0.4 - -
Unit V V V V V V A A A A A A V V V V V V
REF, FB and sOE# Inputs
3-Level Inputs, (TEST, FS, nF[1:0], DS[1:0], PD#/DIV, PE/HD). (These pins are normally wired to VDD, GND, or unconnected) VIN = VDD/GND,VDD = Max; (REF and FB inputs) HIGH, VIN = VDD 3-Level Inputs (TEST, FS, nF[1:0], DS[1:0], PD#/DIV, PE/HD)
3-Level Input DC Current MID, VIN = VDD/2 LOW, VIN = VSS Input Pull-Up Current Input Pull-Down Current Output LOW Voltage VIN = VSS, VDD = Max VIN = VDD, VDD = Max, (sOE#) IOL = 12mA (PE/HD = L/H), (nQ[0:1]) IOL = 20mA (PE/HD = MID),(nQ[0:1]) IOL = 2mA (LOCK) IOH = -12mA (PE/HD = L/H),(nQ[0:1])
VOH IDDQ IDDPD IDD CIN
Output HIGH Voltage
IOH = -20mA (PE/HD = MID),(nQ[0:1]) IOH = -2mA (LOCK)
VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, Quiescent Supply Current Outputs not loaded Power-down Current Dynamic Supply Current Input Pin Capacitance PD#/DIV, sOE# = LOW Test,nF[1:0],DS[1:0] = HIGH; VDD = Max @100MHz
2 25
mA A mA pF
DC Specifications @ 3.3V
Parameter VDD VIL VIH VIHH[11] VIMM[11] VILL[11] IIL Description 3.3 Operating Voltage Input LOW Voltage Input HIGH Voltage Input HIGH Voltage Input MID Voltage Input LOW Voltage Input Leakage Current 3.3V 10% REF, FB and sOE# Inputs Condition Min. 2.97 - 2.0 Max. 3.63 0.8 - Unit V V V V V V A A A A A A
3-Level Inputs VDD- -0.6 - (TEST, FS, nF[1:0], DS[1:0],PD#/DIV, V /2 - 0.3 V /2 + 0.3 DD DD PE/HD); (These pins are normally - 0.6 wired to VDD,GND or unconected VIN = VDD/GND,VDD = Max (REF and FB inputs) HIGH, VIN = VDD MID, VIN = VDD/2 3-Level Inputs, (TEST, FS, nF[1:0], DS[1:0], PD#/DIV, PE/HD) -5 - -50 -200 -25 - 5 200 50 - - 100
I3
3-Level Input DC Current LOW, VIN = VSS
IPU IPD
Input Pull-Up Current Input Pull-Down Current
VIN = VSS, VDD = Max VIN = VDD, VDD = Max, (sOE#)
Note: 11. These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
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CY7B995
DC Specifications @ 3.3V (continued)
Parameter VOL Description Output LOW Voltage Condition IOL = 12 mA (PE/HD = L/H), (nQ[0:1]) IOL = 24 mA (PE/HD = MID),(nQ[0:1]) IOL = 2 mA (LOCK) IOH = -12 mA (PE/HD = L/H),(nQ[0:1]) VOH Output HIGH Voltage IOH = -24 mA (PE/HD = MID),(nQ[0:1]) IOH = -2 mA (LOCK) IDDQ IDDPD IDD CIN Quiescent Supply Current VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, Outputs not loaded PD#/DIV, sOE# = LOW, Test,nF[1:0],DS[1:0] = HIGH, VDD = Max @100 MHz 2.4 2.4 2.4 - 2 Min. - - Max. 0.4 0.4 0.4 - - Unit V V V V V V mA
Power Down Current Dynamic Supply Current Input Pin Capacitance
10(typ.) 230 4
25
A mA pF
AC Input Specifications
Parameter TR,TF TPWC TDCIN FREF Description Input Rise/Fall Time Input Clock Pulse Input Duty Cycle FS = LOW Reference Input Frequency[12] FS = MID FS = HIGH 0.8V - 2.0V HIGH or LOW Condition Min. - 2 10 2 4 8 Max. 10 - 90 50 100 200 MHz Unit ns/V ns %
Switching Characteristics
Parameter FOR VCOLR VCOLBW tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tSKEW5 Description Output frequency range VCO Lock Range VCO Loop Bandwidth Matched-Pair Skew[13] Skew between the earliest and the latest output transitions within the same bank. Skew between the earliest and the latest output transitions among all outputs at 0tU. Skew between the earliest and the latest output transitions among all outputs for which the same phase delay has been selected. Skew between the nominal output rising edge to the inverted output falling edge Skew between non-inverted outputs running at different frequencies Output-Output Skew
[13]
Condition
Min. 6 200 0.25 - -
Max. 200 400 3.5 100 200
Unit MHz MHz MHz ps ps
-
200
ps
Output-Output Skew[13]
- - - -
500 500 500 650
ps ps ps ps
Skew between nominal to inverted outputs running at different frequencies Skew between nominal outputs at different power supply levels
Notes: 12. IF PD#/DIV is in HIGH level (R-reference divider = 1). Reference Input Frequency = FREF. IF PD#/DIV is in MID level (R-reference divider = 2). Reference Input Frequency = FREFx2. 13. Test Load = 20 pF, terminated to VCC/2. All outputs are equally loaded.
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CY7B995
Switching Characteristics (continued)
Parameter tPART tPD0 tODCV tPWH tPWL tR/tF tLOCK tCCJ Description Part-Part Skew Ref to FB Propagation Delay[14] Output Duty Cycle Output High Time Deviation from 50% Output Low Time Deviation from 50% Output Rise/Fall Time PLL lock time[15,16] Cycle-Cycle Jitter Divide by 1 output frequency, FS = L, FB = divide by any Divide by 1 output frequency, FS = M/H, FB = divide by any Fout < 100 MHz, Measured at VDD/2 Fout > 100 MHz, Measured at VDD/2 Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD = 2.5V. Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD = 2.5V. Measured at 0.8V-2.0V for VDD = 3.3V and 0.7V-1.7V for VDD = 2.5V Condition Skew between the outputs of any two devices under identical settings and conditions (VDDQ, VDD, temp, air flow, frequency, etc.) Min. - -250 48 45 - - 0.15 - - - Max. 750 +250 52 55 1.5 2.0 1.5 0.5 100 150 Unit ps ps % ns ns ns ms ps ps
Notes: 14. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5ns between 0.8V-2.0V. 15. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits. 16. Lock detector circuit may be unreliable for input frequencies lower than 4MHz, or for input signals which contain significant jitter.
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CY7B995
AC Timing Definitions
tREF tPWH tPWL
REF
tPD
t0DCV
t0DCV
FB
tCCJ1-12
Q
tSKEWPR tSKEW0,1
tSKEWPR tSKEW0,1
OTHER Q
tSKEW1
tSKEW1
INVERTED Q
tSKEW3
tSKEW3
tSKEW3
REF DIVIDED BY 2
tSKEW1,3,4
tSKEW1,3,4
REF DIVIDED BY 4
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CY7B995
AC TEST LOADS AND WAVEFORMS
VDDQ
Output 20pF Output
150
150
20pF
For Lock Output
Figure 1.
tORISE tOFALL
For All Other Outputs
tORISE tOFALL
2.0V VTH =1.5V 0.8V tPWL
tPWH
1.7V VTH =1.25V 0.7V
tPWH
tPWL
3.3V LVTTL OUTPUT WAVEFORM
2.5V LVTTL OUTPUT WAVEFORM
Figure 2.
1ns
3.0V 2.0V VTH =1.5V 0.8V 0V
1ns
2.5V 1.7V VTH =1.25V 0.7V 0V
1ns
1ns
3.3V LVTTL INPUT TEST WAVEFORM
Figure 3.
2.5V LVTTL INPUT TEST WAVEFORM
Ordering Information
Part Number CY7B995AC CY7B995ACT CY7B995AI CY7B995AIT 44 TQFP 44 TQFP - Tape and Reel 44 TQFP 44 TQFP - Tape and Reel Package Type Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C
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CY7B995
Package Drawing and Dimension
44-lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A44SB
51-85155*A
RoboClock is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7B995
Document History Page
Document Title:CY7B995 Roboclock(R) 2.5/3.3V 200-MHz High-speed Multi-phase PLL Clock Buffer Document Number: 38-07337 REV. ** *A ECN No. 122626 205743 Issue Date 01/10/03 See ECN Orig. of Change RGL RGL New Data Sheet Changed Pin 5 from VDD to VDDQ4, Pin 16 from VDD to VDDQ3 and Pin 29 from VDD to VDDQ1 Added pin 1 indicator in the Pin Configuration Drawing Description of Change
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